Digital data processing systems include one or more processors for performing processing operations in connection with information stored in a memory. Typically, a memory in a modern digital data processing system consists of a hierarchy of storage elements, extending from large-capacity but relatively slow storage elements and various levels of lower-capacity and relatively fast storage devices. The large-capacity and relatively slow devices include such types of devices as disk or tape storage devices which store information on a magnetic medium; such devices are relatively inexpensive on a storage cost per unit of storage basis. Intermediate in the hierarchy, both in terms of speed and storage capacity are random-access memories, which are somewhat faster than the disk or tape devices, but which are also more expensive on a storage cost per unit of storage basis. At the fastest end of the hierarchy are cache memories, which are also the most expensive and thus generally the smallest.
Generally, during processing operations, a processor will enable information to be processed to be copied from the slower devices to the increasingly faster devices for faster retrieval. Generally, transfers between, for example, disk devices and random-access memories are in relatively large blocks, and transfers between the random-access memories and cache memories are in somewhat smaller “cache lines.” In both cases, information is copies to the random-access memory and cache memory on an “as needed” basis, that is, when the processor determines that it needs particular information in its processing, it will enable blocks or cache lines which contain information to be copied to the respective next faster information storage level in the memory hierarchy. Certain prediction methodologies have been developed to attempt to predict the whether a processor will need information for processing before it (that is, the processor) actually needs the information, and to enable the information to be copied to the respective next faster information storage level. However, generally at some point in the processing operations, the processor will determine that information required for processing is not available in the faster information storage level, that is, a “read miss” will occur, and it (that is, the processor) will need to delay its processing operations until the information is available. Generally, the rate at which read misses will occur with storage element(s) at a particular level in the hierarchy will be related to the storage capacity of the storage element(s) at the particular level, as well as the pattern with which the processor accesses the information in the respective storage level. In any case, to enhance the processing efficiency of a digital data processing system, it is generally helpful to be able to assess the effect of changing the capacity of the memory element(s) at a particular level in the memory hierarchy on the rate of read misses at the particular level.